LDMOS device with multiple gate insulating members

An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided be...

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Bibliographic Details
Main Authors LIU MU-YI, YANG ICHEN, CHEN KUAN-PO, LU TAONG, HSU CHIA-LUN
Format Patent
LanguageEnglish
Published 25.01.2011
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An LDMOS device and method of fabrication are provided. The LDMOS device has a substrate with a source region and a drain region formed in the substrate. An insulating layer is provided on a portion of the substrate between the source and the drain region, such that a planar interface is provided between the insulating layer and a surface of the substrate. An insulating member is then formed on a portion of the insulating layer, and a gate layer is formed over part of the insulating member and the insulating layer. By employing such a structure, it has been found that a flat current path exists which enables the on-resistance to be decreased while maintaining a high breakdown voltage.
Bibliography:Application Number: US20080325824