System for integrity protection for standard 2n-bit multiple sized memory devices

An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more command signals, a read data path control signal and one or more write data path control signals in response to an integrity protection control signal and one or more arbitration...

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Bibliographic Details
Main Authors ARNTZEN ESKILD T, ELLIS JACKSON L
Format Patent
LanguageEnglish
Published 05.10.2010
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more command signals, a read data path control signal and one or more write data path control signals in response to an integrity protection control signal and one or more arbitration signals. The second circuit may be configured to write data to a memory and read data from the memory in response to the one or more command signals, the read data path control signal and the one or more write data path control signals. In a first mode, the data may be written and read without integrity protection. In a second mode the data may be written and read with integrity protection, and the integrity protection is written and read separately from the data.
Bibliography:Application Number: US20070754532