Methods and systems for analyzing layouts of semiconductor integrated circuit devices

Disclosed is a method of analyzing layouts of semiconductor integrated circuit devices. The method includes calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest; calculating area-based fault rates of the plurality of layouts...

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Bibliographic Details
Main Authors BAEK GWANG-HYEON, BAE CHOEL-HWYI, CHO MIN-GEON
Format Patent
LanguageEnglish
Published 21.09.2010
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Disclosed is a method of analyzing layouts of semiconductor integrated circuit devices. The method includes calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest; calculating area-based fault rates of the plurality of layouts of interest using the random fault rate, systematic fault rate, parametric fault rate, and area; and selecting layouts of interest to be corrected from among the plurality of layouts of interest using the area-based fault rates of the plurality of layouts of interest.
Bibliography:Application Number: US20070654340