Logic block, a multi-track standard cell library, a method of designing a logic block and an asic employing the logic block

A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standa...

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Bibliographic Details
Main Author PITTS ROBERT L
Format Patent
LanguageEnglish
Published 21.09.2010
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
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Summary:A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standard cells having a first track height and (2) a second row of standard cells adjacent to the first row and having a second track height that differs from the first track height.
Bibliography:Application Number: US20070830696