Method and apparatus for virtual quad-port random access memory
Embedded logic circuits in combination with a configurable logic resources on a common integrated circuit facilitates over-clocked operation of embedded, dual-port memory blocks. The implementation yields fully independent and simultaneous read/write access to the dual-port memory blocks from the co...
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Main Author | |
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Format | Patent |
Language | English |
Published |
14.09.2010
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Subjects | |
Online Access | Get full text |
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Summary: | Embedded logic circuits in combination with a configurable logic resources on a common integrated circuit facilitates over-clocked operation of embedded, dual-port memory blocks. The implementation yields fully independent and simultaneous read/write access to the dual-port memory blocks from the configurable logic on each clock cycle of the configurable logic. Error detection/correction and data scrubbing is also facilitated by the embedded logic circuits, such that error detection/correction is completely transparent to the configurable logic, while data scrubbing is performed with minimal degradation to the memory access bandwidth of the configurable logic. |
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Bibliography: | Application Number: US20050184310 |