Circuit for compression and storage of circuit diagnosis data
A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data output...
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Main Authors | , , , , |
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Format | Patent |
Language | English |
Published |
11.05.2010
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Subjects | |
Online Access | Get full text |
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Summary: | A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value. |
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Bibliography: | Application Number: US20080124196 |