CMOS transistor with a polysilicon gate electrode having varying grain size

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of res...

Full description

Saved in:
Bibliographic Details
Main Authors MILES GLEN L, QUINLIVAN JAMES J, RAMAC SAMUEL C, RICE MICHAEL B, BALLANTINE ARNE W, GILBERT JEFFREY D, CHAN KEVIN K, HOULIHAN KEVIN M, WARD BETH A
Format Patent
LanguageEnglish
Published 11.05.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.
Bibliography:Application Number: US20040904565