SRAM split write control for a delay element

A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal o...

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Bibliographic Details
Main Authors LIU HARRY H L, NELSON DAVID K, GOLKE KEITH W
Format Patent
LanguageEnglish
Published 06.04.2010
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.
Bibliography:Application Number: US20080013856