Hardware memory management unit simulation using concurrent lookups for address translation data

Various technologies and techniques are disclosed for concurrently performing address translation data lookups for use by an emulator. On a first thread, a first lookup is performed for address translation data for use by an emulator. On a second thread, a second lookup for the address translation d...

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Bibliographic Details
Main Author BOND BARRY
Format Patent
LanguageEnglish
Published 23.03.2010
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Various technologies and techniques are disclosed for concurrently performing address translation data lookups for use by an emulator. On a first thread, a first lookup is performed for address translation data for use by an emulator. On a second thread, a second lookup for the address translation data is concurrently and speculatively performed. The address translation data from a successful lookup from either the first lookup or the second lookup is used to map a simulated physical address to a virtual address of the emulator. For example, the first thread can perform a translation lookaside buffer lookup while the second thread concurrently and speculatively performs a page table entry lookup for the address translation data.
Bibliography:Application Number: US20070800707