Self-refresh control circuit and semiconductor memory device including the same

A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh...

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Bibliographic Details
Main Authors HWANG SOO-MAN, LEE HOOL
Format Patent
LanguageEnglish
Published 19.01.2010
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage.
Bibliography:Application Number: US20080031110