Semiconductor memory device and method for erasing the same

A semiconductor memory device includes NAND cell units each having memory cells connected in series, select gate transistors disposed for coupling both ends of the NAND cell unit and dummy cells disposed between the select gate transistors and the memory cells neighbored to them. The dummy cells are...

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Bibliographic Details
Main Author HOSONO KOJI
Format Patent
LanguageEnglish
Published 08.12.2009
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A semiconductor memory device includes NAND cell units each having memory cells connected in series, select gate transistors disposed for coupling both ends of the NAND cell unit and dummy cells disposed between the select gate transistors and the memory cells neighbored to them. The dummy cells are set in a threshold voltage distribution higher than the erased threshold voltage of the memory cell by combination of a first program mode and a second program mode, the first program mode being for boosting the threshold voltage of the dummy cells with a program voltage applied while the second program mode is for boosting the threshold voltage of the dummy cells after reaching a certain threshold level under the condition that the threshold voltage increase is suppressed in comparison with the first program mode.
Bibliography:Application Number: US20070987716