Method of manufacturing complementary metal oxide semiconductor transistors

• Main Authors: WU CHIHIANG, HSU SHIHIEH, HUANG CHENG-TUNG, LIANG CHIA-WEN, WU MENG-YI, TING SHYH-FANN, JENG LI-SHIAN, LEE KUN-HSIEN, CHENG TZYY-MING, HUNG WEN-HAN
• Format: Patent
• Language: English
• Published: 24.11.2009
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.