Method of manufacturing complementary metal oxide semiconductor transistors
A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to...
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Main Authors | , , , , , , , , , |
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Format | Patent |
Language | English |
Published |
24.11.2009
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Subjects | |
Online Access | Get full text |
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Summary: | A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented. |
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Bibliography: | Application Number: US20070779270 |