Method and apparatus for integrated hierarchical electronics analysis

A computer implemented method, apparatus, and computer usable program code for analyzing durability of electronic components. A finite element model for the chassis is created. A set of finite element models for a set of printed wiring assemblies are created, wherein the printed wiring assemblies ar...

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Bibliographic Details
Main Authors TWIGG DAVID W, RASSAIAN MOSTAFA, LEE JUNGUAN
Format Patent
LanguageEnglish
Published 07.07.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A computer implemented method, apparatus, and computer usable program code for analyzing durability of electronic components. A finite element model for the chassis is created. A set of finite element models for a set of printed wiring assemblies are created, wherein the printed wiring assemblies are for use with chassis and include the electronic components. The finite element model for the chassis is combined with the set of finite element models to form a combined finite element model. A finite element analysis of the combined finite element model is performed to form results. The combined model results are transferred to the printed wiring board models. Using the transferred results, stresses and strains are calculated for individual solder joints/leads. A fatigue analysis is performed for the electronic components in the set of printed wiring assemblies based on these stresses and strains, using the results to identify the durability of the electronic components.
Bibliography:Application Number: US20060549819