High performance FET devices and methods thereof

Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impuritie...

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Bibliographic Details
Main Author CHU JACK OON
Format Patent
LanguageEnglish
Published 16.06.2009
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected work function. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.
Bibliography:Application Number: US20080013230