Memory access control device and processing system having same

A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided. From among addresses generated at a read address generation unit and addresses input from an external bus, the address which is supplied to...

Full description

Saved in:
Bibliographic Details
Main Author TAMURA IKUHIRO
Format Patent
LanguageEnglish
Published 19.05.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

Abstract A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided. From among addresses generated at a read address generation unit and addresses input from an external bus, the address which is supplied to a local memory (LM) is selected in accordance with configuration information supplied by a configuration information storage unit. Addresses correspond to ports. Lower bits thereof instruct the storage region inside the LM, and upper bits instruct the LM to be accessed. The read data to be output to a port is selected from among the read data of a plurality of LMs in accordance with the upper bits of this address.
AbstractList A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided. From among addresses generated at a read address generation unit and addresses input from an external bus, the address which is supplied to a local memory (LM) is selected in accordance with configuration information supplied by a configuration information storage unit. Addresses correspond to ports. Lower bits thereof instruct the storage region inside the LM, and upper bits instruct the LM to be accessed. The read data to be output to a port is selected from among the read data of a plurality of LMs in accordance with the upper bits of this address.
Author TAMURA IKUHIRO
Author_xml – fullname: TAMURA IKUHIRO
BookMark eNrjYmDJy89L5WSw803NzS-qVEhMTk4tLlZIzs8rKcrPUUhJLctMTlVIzEtRKCjKB0ll5qUrFFcWl6TmKmQkloF5ibmpPAysaYk5xam8UJqbQcHNNcTZQze1ID8-tbggMTk1L7UkPjTY3NTYzMTS0snImAglACP6Ml8
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
Physics
ExternalDocumentID US7536499B2
GroupedDBID EVB
ID FETCH-epo_espacenet_US7536499B23
IEDL.DBID EVB
IngestDate Fri Jul 19 12:25:39 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US7536499B23
Notes Application Number: US20040557096
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090519&DB=EPODOC&CC=US&NR=7536499B2
ParticipantIDs epo_espacenet_US7536499B2
PublicationCentury 2000
PublicationDate 20090519
PublicationDateYYYYMMDD 2009-05-19
PublicationDate_xml – month: 05
  year: 2009
  text: 20090519
  day: 19
PublicationDecade 2000
PublicationYear 2009
RelatedCompanies SONY CORPORATION
RelatedCompanies_xml – name: SONY CORPORATION
Score 2.7357938
Snippet A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided....
SourceID epo
SourceType Open Access Repository
SubjectTerms CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Title Memory access control device and processing system having same
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090519&DB=EPODOC&locale=&CC=US&NR=7536499B2
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bS8MwFD6MeX3Tqjhv5EH6Vtx6We1DFXpjCLvgVtnbSJYM9rCu2Ir47z1J2-mLPiaBkAS-c06S73wH4J453KKMC8M2GTVs5vQNr-sww5QPDp7LMSZRbItRf5DaL3Nn3oJ1kwujdEI_lTgiImqJeC-Vvc5_HrEixa0sHtgau7bPycyP9OZ2LNWmPD0K_HgyjsahHoZ-OtVHrz5G5X0M7gO01nsYRbsSDPFbIJNS8t8eJTmB_QlOlpWn0BKZBkdhU3hNg8Nh_d-twYEiaC4L7KxBWJzB01CyY78IVbUOSU02J1xI0BOacZJX7H_0SqRSaiYyF1-26EacA0niWTgwcEmL3fYX6XS3eOsC2tk2E5dArJUreo_UcymTxm5FbTzyLudSq8i0bNaBzp_TXP0zdg3H1YeJY_S8G2iX7x_iFv1uye7UiX0Di5-IdQ
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3NT8IwFH8h-IE3RQ342YPZbRHYlztME7YRVDaIbIbb0tKScHAQmTH-976WgV702DZp2ia_917b3_s9gBtmcYMyLnSzw6huMsvW3ZbF9I58cHAdjjGJYlvEdj81nybWpALzTS6M0gn9VOKIiKgp4r1Q9nr584gVKG7l6pbNsWvx0Eu8QNvcjqXalKsFXS8cDYOhr_m-l461-MXDqNzG4L6L1noHI2xHgiF87cqklOVvj9I7hN0RTpYXR1AReR1q_qbwWh32o_K_uw57iqA5XWFnCcLVMdxHkh37RaiqdUhKsjnhQoKe0JyT5Zr9j16JrJWaiczFly36Jk6A9MLE7-u4pGy7_SwdbxdvnEI1X-SiAcSYOaJ9R12HMmnsZtTEI29xLrWKOobJmtD8c5qzf8auodZPokE2eIyfz-Fg_Xli6W33AqrF-4e4RB9csCt1et8dXIto
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Memory+access+control+device+and+processing+system+having+same&rft.inventor=TAMURA+IKUHIRO&rft.date=2009-05-19&rft.externalDBID=B2&rft.externalDocID=US7536499B2