Memory access control device and processing system having same

A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided. From among addresses generated at a read address generation unit and addresses input from an external bus, the address which is supplied to...

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Bibliographic Details
Main Author TAMURA IKUHIRO
Format Patent
LanguageEnglish
Published 19.05.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided. From among addresses generated at a read address generation unit and addresses input from an external bus, the address which is supplied to a local memory (LM) is selected in accordance with configuration information supplied by a configuration information storage unit. Addresses correspond to ports. Lower bits thereof instruct the storage region inside the LM, and upper bits instruct the LM to be accessed. The read data to be output to a port is selected from among the read data of a plurality of LMs in accordance with the upper bits of this address.
Bibliography:Application Number: US20040557096