Variable clocking read capture for double data rate memory devices

A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and sec...

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Bibliographic Details
Main Authors RAO ASHWIN K, SONG SANG-WON
Format Patent
LanguageEnglish
Published 03.03.2009
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A system comprising a first double data rate (DDR) memory device, a second DDR memory device coupled to the first DDR memory device, the second DDR memory device not using a delay locked loop (DLL) device to synchronize clock signals. The system further comprises a logic coupled to the first and second DDR memory devices. The logic is adapted to receive data from the first and second DDR memory devices by way of a single conductive pathway.
Bibliography:Application Number: US20050052371