Methods and structures for protecting one area while processing another area on a chip
Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided whi...
Saved in:
Main Authors | , , , , , , , , , |
---|---|
Format | Patent |
Language | English |
Published |
03.03.2009
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials. |
---|---|
AbstractList | Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials. |
Author | RADENS CARL J KIM DEOK-KEE PFEIFFER DIRK MAHOROWALA ARPAN P DIVAKARUNI RAMACHANDRA CHENG KANGGUO OKORN-SCHMIDT HARALD SETTLEMYER, JR. KENNETH T DALTON TIMOTHY BABICH KATHERINA |
Author_xml | – fullname: DALTON TIMOTHY – fullname: SETTLEMYER, JR. KENNETH T – fullname: OKORN-SCHMIDT HARALD – fullname: KIM DEOK-KEE – fullname: BABICH KATHERINA – fullname: MAHOROWALA ARPAN P – fullname: DIVAKARUNI RAMACHANDRA – fullname: CHENG KANGGUO – fullname: RADENS CARL J – fullname: PFEIFFER DIRK |
BookMark | eNqNyjsOwjAMgOEMMPC6gy_AwkNVVhCIhYnHWlmp20Sq7Ch2xfWhggMw_cP3z92EhWnmnleyKI0CcgNqZQg2FFJopUAuYhQscQefF7AQwiumnkYJpDoKslik8lVhQAgx5aWbttgrrX5dODif7sfLmrLUpBkDMVn9uFU7X_m9P2y2fyxv8qY7Hw |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences Physics |
ExternalDocumentID | US7497959B2 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_US7497959B23 |
IEDL.DBID | EVB |
IngestDate | Fri Aug 30 05:40:33 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_US7497959B23 |
Notes | Application Number: US20040709514 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090303&DB=EPODOC&CC=US&NR=7497959B2 |
ParticipantIDs | epo_espacenet_US7497959B2 |
PublicationCentury | 2000 |
PublicationDate | 20090303 |
PublicationDateYYYYMMDD | 2009-03-03 |
PublicationDate_xml | – month: 03 year: 2009 text: 20090303 day: 03 |
PublicationDecade | 2000 |
PublicationYear | 2009 |
RelatedCompanies | INTERNATIONAL BUSINESS MACHINES CORPORATION |
RelatedCompanies_xml | – name: INTERNATIONAL BUSINESS MACHINES CORPORATION |
Score | 2.7320182 |
Snippet | Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | APPARATUS SPECIALLY ADAPTED THEREFOR AUXILIARY PROCESSES IN PHOTOGRAPHY BASIC ELECTRIC ELEMENTS CABLES CINEMATOGRAPHY CONDUCTORS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY HOLOGRAPHY INSULATORS MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHIC PROCESSES, e.g. CINE, X-RAY, COLOUR,STEREO-PHOTOGRAPHIC PROCESSES PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHOTOSENSITIVE MATERIALS FOR PHOTOGRAPHIC PURPOSES PHYSICS SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES SEMICONDUCTOR DEVICES |
Title | Methods and structures for protecting one area while processing another area on a chip |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090303&DB=EPODOC&locale=&CC=US&NR=7497959B2 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1Ja4NAFH6EdL21tqXpxhyKN2nVidaDFNwIBZPQxJBbGDeSyyhoyd_vc9S0lxbmNA8eM8N8b5l5C8CzyhpPVo8VK6W6QrX8DTGXMkUbszx-ReGQi_4p4dSYRPRjPV4PYNfnwog6oXtRHBERlSDeayGvy59HLE_EVlYv8Q6nivdgaXty7x1beGd12XNsfz7zZq7suna0kKeftkmtpqu2g9L6CK1oswGDv3KapJTyt0YJLuB4jsx4fQmDjEtw5vaN1yQ4Dbv_bglORIBmUuFkB8LqClah6PpcEcZT0tZ__UKnmaD5SbqyC6iPSMEzwtAkJPstIp-UbUZAQ2FcpF211IITRpLtrrwGEvhLd6LgUjeHY9lEi8Om9BsYcmR7CyRnGRoFzNTSWKOJQZmZGzFLNENX00w11RGM_mRz9w_tHs7bjxQdxwMMcXfZI-rjOn4SJ_kNTxORZg |
link.rule.ids | 230,309,783,888,25576,76876 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1JS8NAFH6UutSbVsW6zkFyC5qliTkEIRtRm7bYtPRWJhvtZRJIpH_fl0lavSjMaR48Zob53jLzFoBHidaerBKJRqIqoipnL4i5hIrykGbRMwqHjPdPCcaaP1ffl8NlBza7XBheJ3TLiyMiomLEe8XldfHziOXw2MryKdrgVP7qhaYj7LxjA--sIjiW6U4nzsQWbNucz4Txp6mrRt1V20JpfYAWtl6DwV1YdVJK8VujeKdwOEVmrDqDTsr60LN3jdf6cBy0_919OOIBmnGJky0Iy3NYBLzrc0koS0hT__ULnWaC5idpyy6gPiI5SwlFk5Bs14h8UjQZATWFMp521VBzRiiJ15viAojnhrYv4lJX-2NZzWf7TSmX0GXI9gpIRlM0CqguJ5GsxppK9UyLaCxripSkki4NYPAnm-t_aA_Q88NgtBq9jT9u4KT5VFFw3EIXd5reoW6uont-qt9NYJRZ |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Methods+and+structures+for+protecting+one+area+while+processing+another+area+on+a+chip&rft.inventor=DALTON+TIMOTHY&rft.inventor=SETTLEMYER%2C+JR.+KENNETH+T&rft.inventor=OKORN-SCHMIDT+HARALD&rft.inventor=KIM+DEOK-KEE&rft.inventor=BABICH+KATHERINA&rft.inventor=MAHOROWALA+ARPAN+P&rft.inventor=DIVAKARUNI+RAMACHANDRA&rft.inventor=CHENG+KANGGUO&rft.inventor=RADENS+CARL+J&rft.inventor=PFEIFFER+DIRK&rft.date=2009-03-03&rft.externalDBID=B2&rft.externalDocID=US7497959B2 |