Fuse regions of a semiconductor memory device and methods of fabricating the same

A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation...

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Bibliographic Details
Main Authors CHOI SEUNG-GYOO, BANG JEONG-HO, LEE KUN-GU, SHIN KYEONG-SEON, CHOI HO-JEONG, LYU KYOUNG-SUK, BANG KWANG-KYU
Format Patent
LanguageEnglish
Published 17.02.2009
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.
Bibliography:Application Number: US20050108636