Thermal enhanced upper and dual heat sink exposed molded leadless package

A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar...

Full description

Saved in:
Bibliographic Details
Main Authors JOSHI RAJEEV D, WU CHUNG-LIN
Format Patent
LanguageEnglish
Published 23.12.2008
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.
Bibliography:Application Number: US20050299270