Method for reading a single-poly single-transistor non-volatile memory cell

A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cell is program...

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Bibliographic Details
Main Authors SHEN SHIH-JYE, CHEN HSIN-MING, HSU CHING-HSIANG
Format Patent
LanguageEnglish
Published 26.08.2008
Subjects
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cell is programmed by breaking down the gate dielectric layer. To read the NVM cell, a positive voltage is provided to N drain region, a positive voltage is provided to the gate, and grounding the N source region and the P substrate.
Bibliography:Application Number: US20070625829