Memory array architecture and method for high-speed distribution measurements

A method includes an initial process of selecting a memory cell within the memory array and an operating condition under which the memory cell is to be tested. The memory cell is tested under the specified operating condition, and a measured response obtained therefrom. Based upon the measured respo...

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Bibliographic Details
Main Author ZIPPRICH-RASCH VOLKER
Format Patent
LanguageEnglish
Published 22.07.2008
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

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