Memory array architecture and method for high-speed distribution measurements

• Main Author: ZIPPRICH-RASCH VOLKER
• Format: Patent
• Language: English
• Published: 22.07.2008
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A method includes an initial process of selecting a memory cell within the memory array and an operating condition under which the memory cell is to be tested. The memory cell is tested under the specified operating condition, and a measured response obtained therefrom. Based upon the measured response, a determination is made as to whether the memory cell passes or fails a predetermined criterion. The pass/fail result is communicated to a counter that is integrated on-chip with the memory array, the counter operable to accumulate a total number of pass or fail results supplied thereto. The aforementioned processes are repeated for at least one different memory cell, whereby the new memory cell is tested under the aforementioned operating conditions. Subsequently, a data value representing the accumulated number of pass or fail results is output from the on-chip counter.