Method and apparatus for controlling congestion during integrated circuit design resynthesis

The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the desi...

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Bibliographic Details
Main Authors GASANOV ELYAR E, GALATENKO ALEXEI V, LYALIN ILIYA V
Format Patent
LanguageEnglish
Published 15.07.2008
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field.
Bibliography:Application Number: US20050258738