Method and apparatus for controlling congestion during integrated circuit design resynthesis
The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the desi...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
15.07.2008
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Subjects | |
Online Access | Get full text |
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Summary: | The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field. |
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Bibliography: | Application Number: US20050258738 |