Fine tuning a sampling clock of analog signals having digital information for optimal digital display

Method and system for fine tuning frequency and phase of a sampling clock of analog signals (R, G, B) having digital information, for sampling the analog signals within an optimal sampling period, enabling optimal display by a digital display device ( 92 ). Small amount of information from input sig...

Full description

Saved in:
Bibliographic Details
Main Author YEARIM GADY
Format Patent
LanguageEnglish
Published 24.06.2008
Subjects
ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
CRYPTOGRAPHY
DISPLAY
EDUCATION
PHYSICS
SEALS
Online AccessGet full text

Cover

More Information
Summary:Method and system for fine tuning frequency and phase of a sampling clock of analog signals (R, G, B) having digital information, for sampling the analog signals within an optimal sampling period, enabling optimal display by a digital display device ( 92 ). Small amount of information from input signals is required for rapidly and accurately determining values of frequency and phase of the sampling clock. After measuring using a measurement system ( 96 ) and obtaining pixel values while sweeping phase values of signals using a phase locked loop (PLL) mechanism ( 48 ), there is determining values of two parameters, (i) error of an initial frequency value of the sampling clock (Rx clock), proportional to error of an initial phase locked loop (PLL) division factor value, and (ii) phase of the sampling clock, without need for making additional measurements based on these values, using a control unit ( 94 ).
Bibliography:Application Number: US20040498979