Data processor capable of preventing data overflows and underflows

A data processing apparatus constituting a low-cost audio/video data transmission and reception system is disclosed. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6 . When the size of accumulated data is found to become higher tha...

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Main Authors YOSHIDA HIDEKI, IKEDA KAZUYUKI, SAKUSABE KENICHI, YOSHIKAWA MUNEHIRO, SATO JIN, KAWAGUCHI DAISUKE, NORIZUKI TAKASHI
Format Patent
LanguageEnglish
Published 17.06.2008
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
PICTORIAL COMMUNICATION, e.g. TELEVISION
TRANSMISSION
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Summary:A data processing apparatus constituting a low-cost audio/video data transmission and reception system is disclosed. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6 . When the size of accumulated data is found to become higher than a high threshold, the circuit 21 causes a reception clock generation circuit 8 to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit 8 , an audio/video decoder 7 decodes the audio/video data coming from the reception buffer 6 . This invention applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.
Bibliography:Application Number: US20030432881