Balanced circuit arrangement and method for linearizing such an arrangement
The present invention relates to a balanced circuit arrangement and methods for linearizing and calibrating such a circuit arrangement, wherein linearization is obtained by introducing a load imbalance between the output branches of the balanced circuit arrangement. Thus, a controllable extraneous i...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
26.06.2007
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Subjects | |
Online Access | Get full text |
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Summary: | The present invention relates to a balanced circuit arrangement and methods for linearizing and calibrating such a circuit arrangement, wherein linearization is obtained by introducing a load imbalance between the output branches of the balanced circuit arrangement. Thus, a controllable extraneous imbalance is created between the output loads of the balanced circuit arrangement to thereby obtain a linearization by means of even-order non-linearity. |
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Bibliography: | Application Number: US20060346162 |