Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer

• Main Authors: NANDAKUMAR MAHALINGAM, ADAM LAHIR SHAIK, ZHAO SONG, MEHROTRA MANOJ
• Format: Patent
• Language: English
• Published: 01.05.2007
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER USPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS

The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region ( 102 ). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants ( 104 ). Subsequently, source/drain regions are formed in active regions of an NMOS region ( 106 ). Then, a capped poly layer is formed over the device ( 108 ). A second thermal process is performed ( 110 ) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.