High speed fully scaleable, programmable and linear digital delay circuit

The digitally programmable delay circuit to correct timing skew between data and clock is developed. The digitally programmable delay circuit may be built by cascading delay cells. The delay circuit uses delay cells comprising simple digital elements such as inverters and tri-state inverters to elim...

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Bibliographic Details
Main Authors HAO HONG, CHUNG TAE-SONG, HUI KEVEN
Format Patent
LanguageEnglish
Published 17.04.2007
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:The digitally programmable delay circuit to correct timing skew between data and clock is developed. The digitally programmable delay circuit may be built by cascading delay cells. The delay circuit uses delay cells comprising simple digital elements such as inverters and tri-state inverters to eliminate the intrinsic delay and achieves linearity and monotinicity. The delay cell may be used as a building module which is repeatedly used in a serial fashion. The delay range is fully programmable from the delay of one delay cell to infinity if the chip area is available. The delay range can be scaled by adding more delay cells.
Bibliography:Application Number: US20040879438