All digital reference frequency locking

• Main Authors: CURRIVAN BRUCE J, MILLER KEVIN LEE, KOLZE THOMAS J, BHASKARAN RAVI, LIU HSIN-AN, PUTNAM JEFFREY S, MIN JONATHAN S, LU FANG, LIN THUJI S, CAVALLO JAMES P, LEE TAK K, TAN LOKE KUN, VENKATESAN GOPAL TRIPLICANE
• Format: Patent
• Language: English
• Published: 10.04.2007
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

All digital reference frequency locking. An all digital approach is provided for operation within one or more CMs within a cable modem communication system to lock the upstream of the one or more CMs to the downstream symbol clock provided from a CMTS. The locking of the CM's upstream may be performed using one of at least three different functions: (1) Locking the upstream symbol clock phase to the downstream symbol clock phase, (2) Locking the downstream symbol clock phase to the headend reference clock phase (typically 10.24 MHz or integer multiple thereof), and (3) Locking the upstream carrier frequency to the downstream symbol clock frequency. The all-digital techniques for supporting all digital reference frequency locking functionality provide high performance to support S-CDMA and other synchronous modulation techniques.