Single-stage and multi-stage low power interconnect architectures

An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage d...

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Bibliographic Details
Main Authors YE YIBEN, KHELLAH MUHAMMAD M, DE VIVEK K, KRISHNAMURTHY RAM, ISMAIL YEHEA I, GHONEIMA MAGED M, CAPUTA PETER, TSCHANZ JAMES W
Format Patent
LanguageEnglish
Published 13.03.2007
Subjects
BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
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Abstract An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
AbstractList An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
Author TSCHANZ JAMES W
KRISHNAMURTHY RAM
ISMAIL YEHEA I
GHONEIMA MAGED M
KHELLAH MUHAMMAD M
CAPUTA PETER
DE VIVEK K
YE YIBEN
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– fullname: ISMAIL YEHEA I
– fullname: GHONEIMA MAGED M
– fullname: CAPUTA PETER
– fullname: TSCHANZ JAMES W
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Snippet An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive...
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SubjectTerms BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
Title Single-stage and multi-stage low power interconnect architectures
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