PLL circuit having reduced capacitor size

A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC network having a first resistance and a capacitance and being and RC network coupled to the output of the first charge pump. A second resist...

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Bibliographic Details
Main Authors ROMBACH GERD, MOYAL MIKI
Format Patent
LanguageEnglish
Published 26.12.2006
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
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Summary:A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC network having a first resistance and a capacitance and being and RC network coupled to the output of the first charge pump. A second resistance coupled between the output of the first charge pump and the input to the VCO, the valve of the capacitance C being reduced by a factor X, where V VCO = x C ' ⁢ I CP2 ⁢ t + I CP2 ⁢ R2 VVCO=VCO input voltage Icp2 is the current output by the second charge pump R2=second resistance C'=new capacitance value=C*X C=original capacitance value.
Bibliography:Application Number: US20040979553