Timing based scan chain implementation in an IC design

• Main Authors: HUANG STEVE C, CHEN IHAO
• Format: Patent
• Language: English
• Published: 24.10.2006
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

For use with a design database and a timing database, a computer implemented process for electronic design automation comprising: receiving a netlist that includes cells interconnected by circuit paths, wherein a plurality of the cells are scan cells connected in at least one scan chain; ordering the scan cells according to a prescribed scan cell ordering rule so as to produce a plurality of ordering relationships among scan cells; assigning respective weights from a first category of one or more weights to respective prescribed scan cell order relationships among scan cells of the netlist; assigning respective weights from a second category of one or more weights to prescribed circuit path relationships among cells of the netlist; and determining a physical placement of the cells of the netlist, including the scan cells, using a cost function that places the cells according to the assigned weights.