Method for verifying optimization of processor link

A method for verifying optimization of processor link. First, an initial bus width and an initial bus frequency of a bus coupled between a CPU and a Northbridge are set, such that the bus operates at the initial bus width and the initial bus frequency. Next, a read request for a Southbridge is gener...

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Bibliographic Details
Main Authors PENG SHENGANG, HSU MING-WEI
Format Patent
LanguageEnglish
Published 25.07.2006
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A method for verifying optimization of processor link. First, an initial bus width and an initial bus frequency of a bus coupled between a CPU and a Northbridge are set, such that the bus operates at the initial bus width and the initial bus frequency. Next, a read request for a Southbridge is generated. Next, a bus disconnection signal is output by the Southbridge to disconnect the CPU and the Northbridge when the Southbridge receives the read request. A timer is initialized for calculating an elapsed time value and an optimization verification signal at a first voltage level is generated. Next, a bus connection signal is output by the Southbridge when the elapsed time value reaches a predetermined value. Next, the voltage level of the optimization verification signal is transformed to a second voltage level. Finally, the CPU and the Northbridge are reconnected by the bus according to the bus connection signal, such that the bus operates at another bus operating bus width and another bus operating frequency.
Bibliography:Application Number: US20040825239