Automatic clock gating insertion in an IC design

A computer implemented method is provided for deriving gated clock circuitry in an integrated circuit design, the method comprising: identifying a sequential element associated with a feedback loop in the design; producing a feedback loop signature associated with the feedback loop; wherein the sign...

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Bibliographic Details
Main Authors HUANG STEVE C, FAN YONG, CHEN IHAO
Format Patent
LanguageEnglish
Published 18.07.2006
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A computer implemented method is provided for deriving gated clock circuitry in an integrated circuit design, the method comprising: identifying a sequential element associated with a feedback loop in the design; producing a feedback loop signature associated with the feedback loop; wherein the signature includes an indication of feedback element instance type for each feedback element instance in the feedback loop, feedback position at each instance of a feedback element type in the feedback loop and a control signal for each instance of a feedback element type in the feedback loop; evaluating the feedback loop signature so as to generate associated stimulus logic; generating associated load logic; and inserting the generated stimulus logic to control a clock input to the sequential element; and inserting the generated load logic to provide a data input to the sequential element.
Bibliography:Application Number: US20030435129