Operational amplifier circuit, driving circuit and driving method

In a period T 1 (positive polarity) in which a voltage level of a counter electrode VCOM becomes VC 1 , a data line is driven using P-type operational amplifier OP 1 having P-type driving transistor, while in a period T 2 (negative polarity) in which VCOM becomes VC 2 , the data line is driven using...

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Bibliographic Details
Main Author ISHIYAMA HISANOBU
Format Patent
LanguageEnglish
Published 18.04.2006
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Summary:In a period T 1 (positive polarity) in which a voltage level of a counter electrode VCOM becomes VC 1 , a data line is driven using P-type operational amplifier OP 1 having P-type driving transistor, while in a period T 2 (negative polarity) in which VCOM becomes VC 2 , the data line is driven using N-type operational amplifier OP 2 having N-type driving transistor. An output of a selection circuit for the operational amplifiers OP 1 , OP 2 is set to the high impedance state when VCOM is changed over. At the time of driving the operational amplifier OP 1 , a current which flows in current sources of the operational amplifier OP 2 is cut off, while at the time of driving the operational amplifier OP 2 , a current which flows in current sources of the operational amplifier OP 1 is cut off. In the period before the operational amplifiers OP 1 , OP 2 are driven, the driving transistors of the operational amplifiers OP 1 , OP 2 are turned off. The voltage level of the data line can be changed before driving by positively utilizing the parasitic capacitance between the counter electrode and data line.
Bibliography:Application Number: US20020156019