Link bus between control chipsets and arbitration method thereof

A bus structure is implemented within a control chipset between a first control chip and a second control chip, comprising a first AD bus and a second AD bus. According to an arbitration method implemented to allow a dynamic adjustment of the direction of the AD buses transmission, the first control...

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Bibliographic Details
Main Author PENG SHENGANG
Format Patent
LanguageEnglish
Published 04.04.2006
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A bus structure is implemented within a control chipset between a first control chip and a second control chip, comprising a first AD bus and a second AD bus. According to an arbitration method implemented to allow a dynamic adjustment of the direction of the AD buses transmission, the first control chip has a higher access priority in respect of the first AD bus, while the second control chip has a higher access priority in respect of the second AD bus. When the load of the first AD bus driving by the first control chip is high, a request signal is transmitted from the first control chip to the second control chip, so that if the second control chip is not currently using the second AD bus, the ownership of the second AD bus is handed over to the first control chip to improve the transmission efficiency, and vice versa.
Bibliography:Application Number: US20030617754