Automation of the development, testing, and release of a flow framework and methodology to design integrated circuits

An automated framework and methodology for the development, testing, validation, and documentation of the design of semiconductor products that culminates in the release of a design kit having a flow manager and flow file to actualize a methodology to design a semiconductor product. The flow framewo...

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Bibliographic Details
Main Authors OELTJEN BRET ALAN, AMUNDSON DONALD RAY, PETERSON SCOTT ALLEN, KIRCHNER RICHARD KARL
Format Patent
LanguageEnglish
Published 28.03.2006
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Summary:An automated framework and methodology for the development, testing, validation, and documentation of the design of semiconductor products that culminates in the release of a design kit having a flow manager and flow file to actualize a methodology to design a semiconductor product. The flow framework and methodology receives a methodology and a technology description for the semiconductor product. Then the flow framework and methodology coordinates and tests flow files developed by flow developers using testcases from testcase developers, libraries from library developers and tools from tool from flow developers that may be constantly updated. When a flow file, a testcase, a library, and/or a tool is updated, added, or otherwise changed, ongoing regression testing is accomplished to update the correct flow file. The flow framework and methodology creates a sequence of flows to design the semiconductor product, and each flow, when properly executed, results in a set of deliverables that are input to the next flow. The flows include not only the evolution of the design from a high-level behavioral description to a physical implementation, but also the verification of the specified functions and of manufacturability. Delivered to the customer is a design kit having the tested and validated flow files, along with the flow manager that executes the flow files. Using the design kit, a designer of a semiconductor product can input her/his chip specification; output will be final testable and verifiable design views for a manufacturing facility of the semiconductor product.
Bibliography:Application Number: US20030435168