Incremental automata verification

Methods and apparatus for performing formal verification of a system defined by a set of automata are useful in facilitating computing efficiencies during the verification of an incremental system design. The various embodiments permit computing efficiencies by saving information generated during a...

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Bibliographic Details
Main Authors GOLDMAN ROBERT P, MUSLINER DAVID J, PELICAN MICHAEL J
Format Patent
LanguageEnglish
Published 18.10.2005
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Methods and apparatus for performing formal verification of a system defined by a set of automata are useful in facilitating computing efficiencies during the verification of an incremental system design. The various embodiments permit computing efficiencies by saving information generated during a verification of the system for use in subsequent verification runs. The saved information includes calculation results pertaining to instances or elements of the system that do not require modification for the next subsequent verification.
Bibliography:Application Number: US20010015058