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An electronic device packaging assembly ( 10 ) that includes a ball grid array ( 60 ) and specialized construction to be able to operate from DC up to 50 GHz with minimal parasitic losses. The packaging assembly ( 10 ) includes a thin base plate ( 14 ) made of a suitable rigid material. Power vias (...

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Bibliographic Details
Main Authors DIN SALAH, CROSSMAN BRIAN F, HATHAWAY JAMES A
Format Patent
LanguageEnglish
Published 23.08.2005
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An electronic device packaging assembly ( 10 ) that includes a ball grid array ( 60 ) and specialized construction to be able to operate from DC up to 50 GHz with minimal parasitic losses. The packaging assembly ( 10 ) includes a thin base plate ( 14 ) made of a suitable rigid material. Power vias ( 48 ), signal vias ( 26 ) and ground vias ( 46 ) are formed through the base plate ( 14 ) to be coupled to traces, circuit components, and/or the device ( 12 ) within the packaging assembly ( 10 ). An impedance matching compensation network ( 28 ) provides impedance matching between the device ( 12 ) and the signal vias ( 26 ). The ball grid array ( 60 ) includes a plurality of solder balls ( 68 ), including ground solder balls ( 72 ), signal solder balls ( 74 ) and power solder balls ( 76 ), electrically coupled to the appropriate via extending through the base plate ( 14 ).
Bibliography:Application Number: US20030611340