Yield improvement through probe-based cache size reduction

A multiple-way cache memory having a plurality of cache blocks and associated tag arrays includes a select circuit that stores way select values for each cache block. The way select values selectively disable one or more cache blocks from participating in cache operations by forcing tag comparisons...

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Bibliographic Details
Main Authors CHERABUDDI RAJASEKHAR, KASINATHAN MEERA
Format Patent
LanguageEnglish
Published 12.07.2005
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A multiple-way cache memory having a plurality of cache blocks and associated tag arrays includes a select circuit that stores way select values for each cache block. The way select values selectively disable one or more cache blocks from participating in cache operations by forcing tag comparisons associated with the disabled cache blocks to a mismatch condition so that the disabled cache blocks will not be selected to provide output data. The remaining enabled cache blocks may be operated as a less-associative cache memory without requiring cache addressing modifications.
Bibliography:Application Number: US20010839057