Method and apparatus for testing a CAM addressed cache

In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to dr...

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Bibliographic Details
Main Authors MILLER JAY B, CLARK LAWRENCE T
Format Patent
LanguageEnglish
Published 21.06.2005
Edition7
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:In one embodiment, an array of content addressable memory (CAM) cells include a first plurality of CAM cells and a second plurality of CAM cells. The second plurality of CAM cells has a width sufficient to address a height of the array. A first plurality of CAM drivers are coupled to the array to drive the first plurality of CAM cells. The first plurality of CAM drivers prevent the first plurality of CAM cells from participating in a match when the array is in a test mode.
Bibliography:Application Number: US20040803408