Parallel data communication consuming low power
In one example embodiment involving a high-speed parallel-data communication from a first module to a second module, a termination circuit is adapted to reduce power consumption at the second module. The termination circuit includes resistive circuits respectively coupled to a plurality of parallel...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
22.02.2005
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | In one example embodiment involving a high-speed parallel-data communication from a first module to a second module, a termination circuit is adapted to reduce power consumption at the second module. The termination circuit includes resistive circuits respectively coupled to a plurality of parallel data-carrying lines that form the data bus. The other ends of the resistive circuits are interconnected to provide a reference voltage using the data on the parallel data-carrying lines. Consistent with one embodiment of the present invention, the communication approach uses data sets encoded so that each data set includes the same number of ones and zeroes; in this manner the reference voltage is always at midpoint and useful in providing termination to the data-carrying lines at all times. |
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Bibliography: | Application Number: US20010871160 |