Semiconductor chip package and method of fabricating same

A semiconductor chip package and a method of fabricating a semiconductor chip package provide a reduced chip size package. The semiconductor chip package includes a semiconductor chip; a plurality of pads disposed on an upper surface of the semiconductor chip; a thermosetting resin formed on the upp...

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Bibliographic Details
Main Author CHOI KWANG SUNG
Format Patent
LanguageEnglish
Published 15.02.2005
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A semiconductor chip package and a method of fabricating a semiconductor chip package provide a reduced chip size package. The semiconductor chip package includes a semiconductor chip; a plurality of pads disposed on an upper surface of the semiconductor chip; a thermosetting resin formed on the upper surface of the semiconductor chip such that through-holes in the thermosetting resin expose the pads; a multi-layer wiring pattern formed on the thermosetting resin; a connecting unit electrically connecting the multi-layer wiring pattern with the pads; a solder resist on the thermosetting resin, the multi-layer wiring pattern and the connecting unit, such that at least one through-hole in the solder resist exposes a portion of the multi-layer wiring pattern; and a solder ball mounted on the through-hole of the solder resist in contact with the exposed portion of the metal pattern.
Bibliography:Application Number: US20020232652