Apparatus for information recording and reproducing

In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a ph...

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Bibliographic Details
Main Authors NAKAI NOBUAKI, IDE HIROSHI, TAKASHI TERUMI, SUZUMURA SHINTARO, NISHIYA TAKUSHI, YAMAKAWA HIDEYUKI, KATO TAKATOSHI, NARA TAKASHI
Format Patent
LanguageEnglish
Published 14.09.2004
Edition7
Subjects
INFORMATION STORAGE
INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER
PHYSICS
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Summary:In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
Bibliography:Application Number: US20010793924