Crosstalk analysis method, method for designing/manufacturing electronic circuit device by using the same, and recorded medium of electronic circuit library therefor

• Main Author: SASAKI YASUHIKO
• Format: Patent
• Language: English
• Published: 03.08.2004
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

This is a method for more accurately calculating delay times in an electronic circuit device wherein signal arrival times on a victim wire and a plurality of aggressor wires adjacent thereto dynamically vary dependent on an input signal pattern by analyzing values of crosstalk-deriving delay degradation occurring between those wires. By utilizing delay degradation information searchable according to relative signal arrival times between the victim wire and the aggressor wires and adding delay degradations arising between the victim wire and the aggressor wires, calculated at every signal arrival time on the victim wire, the total delay degradation in the presence of a plurality of aggressor wires is calculated. Designing of a high-speed and large-scale electronic circuit device is facilitated and, because a superfluous margin regarding delay times can be eliminated, such electronic circuit devices can be efficiently designed and manufactured.