Fail-safe zero delay buffer with automatic internal reference
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a first reference signal and generate a second reference signal. A frequency and a phase of the second reference signal may be (i) adjusted in response to the first reference signal and (ii)...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
27.07.2004
|
Edition | 7 |
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to receive a first reference signal and generate a second reference signal. A frequency and a phase of the second reference signal may be (i) adjusted in response to the first reference signal and (ii) held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled and/or substantially zero delay with respect to the first reference signal. |
---|---|
Bibliography: | Application Number: US20010928818 |