Fractional-frequency-modulation PLL synthesizer that suppresses spurious signals

The phase comparator in a phase locked loop synthesizer has a identical first and second transmission gates connected to a front row and a back row of 2N-1 gate delay elements, respectively. Third and fourth transmission gates are permanently set to an ON setting. The first transmission gate and NAN...

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Bibliographic Details
Main Author KAWAHARA TADASHI
Format Patent
LanguageEnglish
Published 11.05.2004
Edition7
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER
ELECTRICITY
MODULATION
PULSE TECHNIQUE
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Summary:The phase comparator in a phase locked loop synthesizer has a identical first and second transmission gates connected to a front row and a back row of 2N-1 gate delay elements, respectively. Third and fourth transmission gates are permanently set to an ON setting. The first transmission gate and NAND gates operate as a gate delay element when a COUNT signal is at a low logical level and operate as a ring oscillator when the COUNT signal is at a high logical level.
Bibliography:Application Number: US20020283119