Enhanced bus arbiter utilizing variable priority and fairness
A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals bas...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
06.04.2004
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal. |
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Bibliography: | Application Number: US19990363947 |